The present invention relates to circuits and associated methods for monitoring current in a load, and, more particularly to a circuit for detecting the current delivered to a load by a power transistor, with reduced noise sensibility.
Circuits for detecting the current circulating in a load are commonly associated with output power stages and are necessary components for implementing a desired control and regulation. According to common switching mode driving techniques, current is fed to a load through one or more power transistors (switches) coupling the load to the supply.
For sake of simplicity, consider the case in which a load is driven through a high-side N-channel power MOS transistor, although the following discussion is also applicable to the case of a load driven by a power device of a different kind and/or in a different configuration. A typical circuit used for sensing the current circulating in the load is the one depicted in FIG. 1. A load connected to an output node OUT is coupled to the supply node VS via a power transistor 1, (NMOS_POWER). Usually, an sense transistor 2, NMOS_POWERxe2x80x94SENSE, producing a replica current scaled by a factor n of the current circulating in the true power device NMOS_POWER, is associated to it. Such a sense transistor is of the same type of and connected in parallel to the power transistor but has a much smaller size than the latter.
The value of the current circulating in the load can be determined by sensing with a differential amplifier 4 (DIFF_AMPL), the voltage drop on a sensing resistance 3 (RSENSE) connected in series to the sense transistor 2. Resistor 3 must be dimensioned in function of the design current that circulates in it and to the expected voltage drop on it and it must have a resistance smaller than the interval resistance RON of the sense transistor 2. The order of magnitude of the voltage drop on the nodes of the sensing resistance 3 may be of tens or hundreds of millivolts and is normally sensed via an operational amplifier 4.
The degree of precision of this solution is rather coarse. In fact the voltage sensed on the resistance 3 is sensible to the process spread of the values of the resistance 3 and of RON of transistor 2. Burdensome trimming operations, when testing the device, are required to obtain a precision of at least 1%. Moreover, the amplifier 4 is sensitive to substrate noise even if subject to relatively small current injections, that may unbalance the input differential stage causing large variations of the output.
Consider, for example, the case of the half-bridge architecture of FIG. 2, that is the architecture typically used for driving a load via two DMOS power transistors. When the DMOS 6 is turned on and the DMOS 7 is turned off, the current on the external inductor increases as shown in FIG. 2. On the contrary, when the DMOS 6 is turned off, the current circulates in the intrinsic diode, constituted by the drain diffusion of the DMOS and the P type substrate, and in diode 8 constituted by the N type drain diffusion of the DMOS and the P type body diffusion.
The turning on of the diode 9 may cause the turn on of the parasitic NPN transistor 10 depicted in FIG. 3, whose emitter is constituted by the N type drain diffusions of the DMOS, whose base is constituted by the P type diffusion of the substrate and whose collectors are the N type epitaxial regions. If, for example, the amplifier 4 has a PNP input stage, because the base of the PNP transistors of the comparator coincides with the epitaxial regions, a current injected by the parasitic transistor 10 in this base region may unbalance the differential amplifier 4 of the architecture of FIG. 1.
Another drawback affecting this circuit includes the fact that it is not immune from the current spikes that are produced when the NMOS_POWER_H_SIDE transistor turns on. Referring to FIG. 4, should the DMOS 6 turn on while current is recirculating in diodes 8 and 9, the charges stored in diodes 8 and 9 (xe2x80x9cstorage chargesxe2x80x9d) are discharged producing a current spike, whose direction is depicted in FIG. 5. These current spikes last several hundreds of nanoseconds and must be masked, to prevent generation of relevant undesired effects at the output. To this end, blanking circuits must be added for blocking the differential amplifier 4 of FIG. 1 during this phase, or the amplifier 4 should have a slow response.
In the first case there is a time interval in which there is no signal for controlling the current delivered to the load. In the second case it is necessary to choose an amplifier having a dynamic response sufficiently slow to make it substantially insensitive to current spikes, though sufficiently fast to effectively track normal load variations.
It is an object of the invention to provide a circuit for monitoring the current delivered to a load that is not burdened by the above mentioned drawbacks, and that couples an outstanding precision even in presence of a considerable process spread to an excellent dynamic response.
Different from known circuits, the circuit of the invention does not require the introduction of a masking interval, that limits the speed of intervention of the circuit. In fact, the circuit of this invention has a fast dynamic response capable of following the variations of the current being delivered to the load, though it is relatively insensitive to the exceptionally fast variations due to spurious current spikes.
According to the invention, these results are achieved by coupling a disturbances attenuating circuit to the sense transistor and to the power transistor driving the load. The disturbances attenuating circuit is able to produce a current signal proportional to the current circulating in the load that is relatively free of disturbances. According to a preferred embodiment, the disturbances attenuating circuit is realized with MOS transistors.
The circuit of the invention may be used in a monitoring system for detecting eventual overcurrents circulating in a load driven by a power transistor. Such a system is obtained by connecting in cascade to the disturbances attenuating circuit a comparator that compares the current signal produced by the disturbances attenuating circuit with a threshold current. The comparator produces a warning logic signal whenever the signal surpasses the threshold.
A further object of the invention is to provide a system for regulating the current delivered to the load, realized by connecting in cascade to the disturbances attenuating circuit a trans-impedance amplifier, input with the current signal produced by the disturbances attenuating circuit and with a reference signal and producing a driving signal of the power transistor that drives the load.